1. Field of the Invention
The present invention relates to a semiconductor device and a method of production of the same, more particularly relates to a technique useful for reducing the size of a semiconductor device.
2. Description of the Related Art
In the past, a semiconductor device to be mounted on a motherboard has been comprised of a semiconductor chip mounted on a wiring board called an xe2x80x9cinterposerxe2x80x9d. This interposer has been considered necessary for aligning the positions of the electrode terminals of the semiconductor chip and motherboard.
If an interposer is used, however, the thickness of the semiconductor device increases by the amount of that thickness, so it is preferable not to use such an interposer as much as possible so as to meet with the recent demands for reducing the size of electronic equipment.
Therefore, in recent years, effort has been underway to develop a semiconductor device not requiring an interposer. A sectional view of such a semiconductor device of the related art is shown in FIG. 12A.
The semiconductor device 101 of the related art is mainly comprised of a silicon substrate 102 and does not have an interposer. One surface 102a of the silicon substrate 102 has formed on it an electronic element formation layer 103 including a transistor or other electronic element. This is electrically connected with a via hole electrode pad 110. An insulating film 104 prevents electrical connection of the via hole electrode pad 110 or main electrode pad 105 with the silicon substrate 102.
The semiconductor element formation layer 103 and via hole electrode pad 110 have stacked over them an SiO2 film 106 and an interconnection pattern 107. The SiO2 film 106 has a via hole 106a opened in it. The interconnection pattern 107 and via hole electrode pad 110 are electrically connected through this opening.
The via hole electrode pad 110 is provided integrally with the main electrode pad 105. Further, the main electrode pad 105 and the silicon substrate 102 under it have a through hole 102c opened in them.
The through hole 102c is a characterizing feature of this type of semiconductor device and is provided to lead out the interconnection pattern 107 to the other surface 102b of the silicon substrate 102. The interconnection pattern 107 led out to the other surface 102b is provided with solder bumps 108 functioning as external connection terminals to be aligned in position with the terminals of the motherboard (not shown).
FIG. 12B is a plan view of the semiconductor device 101 seen from the direction of the arrow A of FIG. 12A. For convenience in explanation, the interconnection pattern 107 is omitted.
The via hole 106a is a wide diameter circle at the bottom of which the via hole electrode pad 110 is exposed.
The semiconductor device 101 is fabricated by building in a structure new to the existing semiconductor device (LSI etc.) 109 shown in section in FIG. 12C. As will be explained using FIG. 12C, the main electrode pad 105 is provided at the existing semiconductor device 109 as well. This is the location where originally bonding wires, stud bumps, etc. are bonded, signals are input and output, and power is supplied.
On the other hand, the via hole electrode pad 110 (FIG. 12B) is one of the new structures and is not provided in existing semiconductor devices 109. The via hole electrode pad 110 is newly provided to increase the contact area with the interconnection pattern 107 (FIG. 12A) by providing a wide-diameter via hole 106a above it and to prevent peeling with the interconnection pattern 107 due to stress and poor electrical contact arising due to the same.
In this way, in the semiconductor devices of the related art, in addition to the originally present main pad 105, a via hole pad 110 is newly provided as a part for electrical connection with the interconnection pattern 107 and, to ensure reliable electrical connection, a wide-diameter circular via hole 106a is opened above the via hole electrode pad 110.
If this via hole electrode pad 110 is newly provided, however, the planar size of the semiconductor device 101 becomes that much larger. This runs counter to the trend toward smaller sizes of semiconductor devices.
Further, providing the via hole electrode pad 110 in addition to the existing main electrode pad 105 requires that the design of existing semiconductor devices be changed, so places a large burden on manufacturers of semiconductor devices (semiconductor manufacturers).
An object of the present invention is to provide a semiconductor device, and a method of production of the same, enabling reliable electrical connection between an electrode pad and interconnection pattern without separate provision of a via hole use electrode pad in addition to the existing main electrode pad.
To achieve the object, according to a first aspect of the present invention, there is provided a semiconductor device comprised of a semiconductor substrate; an electronic element formed on one surface of the semiconductor substrate; an electrode pad formed on that one surface and electrically connected with the element; a through hole passing through the electrode pad and the semiconductor substrate; an insulating film formed on at least the other surface of the semiconductor substrate, an inner wall of the through hole, and the electrode pad; a via hole provided in the insulating film on the electrode pad along an opening rim of the through hole; and an interconnection pattern electrically leading out the electrode pad to the other surface of the semiconductor substrate through the through hole and the via hole.
Preferably, the via hole is ring shaped.
Alternatively, preferably the via hole is arc shaped and a plurality of the via holes are provided.
Alternatively, preferably the via hole is dot shaped and a plurality of the via holes are provided.
Preferably, a diameter of the through hole is larger at a portion passing through the electrode pad than a portion passing through the semiconductor substrate.
Preferably, the electrode pad has a bottom electrode pad comprised of a first metal and a top electrode pad comprised of a second metal having a higher melting point than the first metal and formed on the bottom electrode pad. More preferably, the first metal is aluminum and the second metal is copper.
Preferably, the interconnection pattern electrically leads out the electrode pad to the one surface of the semiconductor substrate as well. It is possible to stack a plurality of these semiconductor devices together and electrically connect interconnection patterns of facing surfaces of each bottom semiconductor device and top semiconductor device through external connection terminals.
In one embodiment, the through holes are filled by a conductor electrically connected with the interconnection patterns. It is possible to stack a plurality of these semiconductor devices and electrically connect conductors filled in corresponding through holes of each bottom semiconductor device and top semiconductor device through external connection terminals.
According to a second aspect of the invention, there is provided a method of production of a semiconductor device comprising the steps of forming an electronic element on one surface of a semiconductor substrate; forming an electrode pad electrically connected with the element on the one surface of the semiconductor substrate; forming a through hole passing through the electrode pad and the semiconductor substrate; forming an insulating film on at least the other surface of the semiconductor substrate, an inner wall of the through hole, and the electrode pad; forming a via hole exposing part of the electrode pad along an opening rim of the through hole by patterning the insulating film; forming a conductive film on the insulating film and in the via hole; and forming an interconnection pattern electrically leading the electrode pad to the other surface of the semiconductor substrate through the through hole and the via hole by patterning the conductive film.
Preferably, the step of forming a through hole includes the steps of forming a first opening in the electrode pad by patterning and forming a second opening in the semiconductor substrate including the element by firing through the first opening a laser beam of a smaller diameter than the diameter of the first opening, the through hole being defined by the first opening and the second opening.
More preferably, the step of forming the first opening and the step of forming the second opening include between them a step of polishing the other surface of the semiconductor substrate to reduce the thickness of the semiconductor substrate.
Preferably, the step of forming the via hole is performed by opening the insulating film by a laser beam.
More preferably, a ring-shaped via hole is formed by firing the laser beam on the insulating film in a ring shape.
Still more preferably, the step of forming an electrode pad includes the steps of forming a bottom electrode pad comprised of a first metal and forming a top electrode pad comprised of a second metal having a higher melting point than the first metal on the bottom electrode pad. Preferably, aluminum is used as the first metal and copper as the second metal.
In one embodiment, by the step of forming the interconnection pattern, the interconnection pattern is formed so that the electrode pad is electrically led out to the one side of the semiconductor substrate as well. It is possible to provide the steps of preparing a plurality of such semiconductor devices and stacking the semiconductor devices in a plurality of layers by electrically connecting the interconnection patterns of the semiconductor device through external connection terminals.
In one embodiment, the method includes a step of filling the through holes by a conductor electrically connected to the conductive film after the step of forming the conductive film. It is possible to provide the steps of preparing a plurality of such semiconductor devices and stacking the semiconductor devices in a plurality of layers by electrically connecting the conductors exposed from openings of corresponding through holes of the plurality of semiconductor devices through external connection terminals.